发明名称 PROGRAMABLE DIVIDER
摘要 PURPOSE:To ensure a high-speed and accurate operation by leading out the control signal with the division ratio data of the fixed digit number which is set by the BCD code through coation of the high- and low-speed division steps. CONSTITUTION:High-speed division step A, B and C consist of 1st to 3rd dividers 12, 13, 19, 21, 29, 30 and 31 which divide sequentially the input pulse signals into two parts with the vertical connection relation, 1st pulse control circuit A which samples one pulse from the input pulse signal, 2nd pulse control circuit B which samples one or two pulses from the output pulse of the 1st divider, and 3rd pulse control circuit C which samples one or two pulses from the output pulse of the 2nd divider respectively. While low-speed division step D comprises divider 4 which operates according to the division ratio data of the higher-order digit, and frequency extender 48 and 46 which deliver the control signal to drive the 1st to 3rd pulse control circuits with every division cycle of divider 48. Thus, the control signal, which is to be the output divided by the division ratio data of the fixed digit number of the BCD code and through the coaction of division steps A-D, is led out as the output.
申请公布号 JPS54102959(A) 申请公布日期 1979.08.13
申请号 JP19780009777 申请日期 1978.01.31
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 KOJIMA TADASHI
分类号 H03K23/64;H03J5/02;H03K23/66;H03L7/183;H03L7/193;(IPC1-7):03K21/36 主分类号 H03K23/64
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