发明名称 READ*WRITE CONTROL SYSTEM FOR MEMORY UNIT
摘要 PURPOSE:To make it possible to correct automatically an error in a memory unit stored with data consisting of (m)-bit words by using the (m)-number memory elements where (n) bits are simultaneously read and written, by processing data with word constitution at read time different from that at write time. CONSTITUTION:Memory unit 1 consists of the (m)-number, e.g. 39 memory elements where (n), e.g. four bits are simultaneously read and written. In read operation, address register 7 as-signal an address to read four word of 39 bits, bit selector circuits 6-1 to 6-39 selects one word among four, and one word consisting of 39 bits inclinding one-bit error correction code for seven bits is stored in data register 3. In write operation, write data are recomposed in word constitution different from that in read processing and written to data register 3 being separated into m/n pieces (four time in the above-mentioned case). Consequently, an error can be detected and corrected accurately even if one of memory element would be in trouble.
申请公布号 JPS5533276(A) 申请公布日期 1980.03.08
申请号 JP19780106483 申请日期 1978.08.31
申请人 FUJITSU LTD 发明人 KINUGASA KOUICHIROU
分类号 G06F12/16;G06F13/00;G11C7/00;G11C29/00 主分类号 G06F12/16
代理机构 代理人
主权项
地址