| 摘要 |
Disclosed is an information processor provided with a main memory device capable of simultaneously reading or writing 2N bit data. 2N bit data read out from the main memory device is applied to a selector through a memory bus of 2N-bit construction. The selector devides the data comprising 2N bits in two N-bit units and then outputs that data into a scratch pad memory device constituted by N bits X M addresses. The data written in the scratch pad memory device in N bit units is processed by a central processing unit of N-bit architecture. For accessing the operand, the information processor accesses the main memory in N-bit units. |
