| 摘要 |
1379838 Semi-conductor devices FUJITSU Ltd 18 Sept 1972 [18 Sept 1971 27 Dec 1971 28 Dec 1971 15 June 1972] 43182/72 Heading H1K A P-channel IGFET having transistor regions 82, 83 comprising enhancement and depletion modes (Fig. 3) is manufactured from a substrate 81 on N-type Si on which an insulant film 84 of SiO 2 and a further insulant film of Si 2 N 4 are deposited; the latter having lower impurity diffusion properties. Windows are etched therein and source and drain electrodes 86 and gate electrodes 87 are deposited thereon, and source and drain region 88, 89, 90 are P-diffused to form first and second FET's 82, 83 series connected through common electrode 86. Transistor 82 is of depletion mode wherein the diffused impurity produces a conductivity type similar to regions 88, 89, 90, but transistor 83 is of enhancement mode wherein the impurity produces an opposite conductivity type. Initially the SiO 2 insulant film 84 is formed on the substrate and the Si 3 N 4 films formed to overlay the gate insulant film of transistor 82, after which polycrystalline layers 87 are deposited on the gate insulant films. Thereafter B impurity is diffused into the assembly, and easily penetrates the films 87 and the thin SiO 2 film, but not the Si 3 N 4 film; the transistor element of which assumes the enhancement mode while the other element assumes a depletion mode by reason of the diffusion of B into the gate insulant film to establish an electric field influencing the substrate 81 lying thereunder. In a modification (Fig. 4, not shown) a N-type Si semi-conductor is oxidized thermally to a SiO 2 gate insulant film on its surface, a Si 3 N 4 film is formed thereon, and selectively removed at an area overlying the gate region of the depletion mode transistor element. A polycrystalline Si layer is deposited over the substrate and the films thereon, and is selectively etched out except where it overlies the gate regions, the remaining layer being used for an etching mask to expose the substrate at the P-type boron indiffusion layers. Transistor elements with the SiO 2 and Si 3 N 4 films are of enhancement mode and negative threshold voltage, while the elements with the SiO 2 film are of depletion mode and have positive threshold voltage. Silicon oxide films surround the polycrystalline gate electrodes and source and drain electrodes are provided to contact the respective source and drain regions to complete the enhancement depletion element. Alternatively the gate electrodes may be of Al, with impurity diffusion prior to their formation. In similar modifications (Figs. 5, 6, not shown) comprising enhancement and depletion FET elements simultaneously formed on the same substrate, gate insulant films are formed in the position of the polycrystalline gate electrodes of the respective elements, and an insulant film resistant to impurity diffusion is formed on the gate insulant film of one element prior to the impurity diffusion; the impurity, e.g. B is diffused into the substrate surface through the gate insulant film of one transistor element to change the impurity concentration in the substrate, and is not so diffused in the other transistor element. The device thus embodies an enhancement FET in series with a depletion FET as load resistor with a common sourcedrain. The gate electrodes may alternatively be of Al with prior impurity diffusion. Introduction of impurities, e.g. B may be by predeposition of B 2 O 3 on the substrate as a diffused layer from BBr 3 and dry O 2 , followed by drive-in thermal reduction pretreatment with wet O 2 during thermal diffusion; which is followed by further thermal diffusion in dry N 2 . The process is described in detail for the introduction of the impurity as an immobile negative charge in the gate insulant films, and for diffusion of the impurity through the gate insulant films into the semi-conductor substrate; the films being of two distinct kinds or thicknesses. |
