Hybrid programmable many-core device with on-chip interconnect

摘要

The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.

主权项

1. A hybrid programmable logic device, comprising:
programmable logic elements, at least some of which provide at least one hardware acceleration function; processors interleaved with the programmable logic elements and physically sized such that one physical dimension of each of the processors is equal to a multiple of a same physical dimension of the programmable logic elements; and first intersecting horizontal and vertical connectors that provide data to and from the programmable logic elements, the processors or any combination therein; wherein the vertical pitch of the intersecting horizontal and vertical connectors is a multiple of a vertical pitch of at least one of the programmable logic elements of the processors.