| 摘要 |
PURPOSE:To improve the efficiency of utilization of a memory by increasing the potential difference between pieces of information H and L by using a capacity of potential dependency for cell capacity and by driving the capacitor via a storage word line. CONSTITUTION:Bit line Bi and word line W are taken as a row and column respectively and memory cells are provided near respective intersections between rows and columns to form cell matrixes 2 and 2' provided with parallel storage word lines Z pairing with word lines. Further, this unit is equipped with sense amplifiers 3 and 30 as many as rows, X decoder 10 selecting a pair of lines W and Z, input- output circuits 5 and 50 for lines B, and Y decoder 4. Then, the cell has cell capacity Cso8 depending upon selection gate GT and MOSFET and Cso8 varies in value with the voltage difference between its gate electrode and source-drain electrode; and the potential of line Z rises high when line W is at the low potential and falls low when at the high potential. |
