Driving structure of liquid crystal display panel, liquid crystal display panel, and driving method thereof

摘要

The present disclosure discloses a driving device for liquid crystal display panel, a liquid crystal display panel, and a driving method thereof, said driving device comprising: a plurality of scanning lines, a first control circuit, a second control circuit, and a third control circuit. According to the present disclosure, three control circuits are added to the driving device of the liquid crystal display panel, whereby normal two dimensional display can be realized without additional cost being added therein. The black frame insertion technology for eliminating the cross-talk phenomena during three dimensional display can be used, i.e., the dual-gates, which are used for reducing the influence of high frame rate on the charging of the liquid crystal panel, can be turned on simultaneously.

主权项

1. A driving device for liquid crystal display panel, comprising:
a plurality of scanning lines; a first control circuit, configured to control the transmission of scanning signals of all odd-numbered scanning lines of said plurality of scanning lines; a second control circuit, configured to control the transmission of scanning signals of all even-numbered scanning lines of said plurality of scanning lines; and a third control circuit, configured to realize different connection states in each pair of scanning lines, which consists of an odd-numbered scanning line and a corresponding even-numbered scanning line, of said plurality of scanning lines under different display modes, said display modes comprising two dimensional display mode and three dimensional display mode, wherein said third control circuit comprises:
a third specified number of switching transistors, each switching transistor being connected between the odd-numbered scanning line and the even-numbered scanning line of a corresponding pair of scanning lines respectively; anda third control signal line, configured to control the on/off state of each switching transistor, said third control signal line being connected to the gate of each of said third specified number of switching transistors.