Programmable pulse length tester for ATE - uses registers in cascade for memorising pulse sequence for comparison with reference

摘要

The device has a digitally programmed memory (1) that transfers predetermined interval values to two pulse generators (3,4) via a bus (10). The generators comprise a number of registers in cascade. A clock (4) provides the unit of time to be used in defining these intervals. Several registers in a signal memory system (5) memorise the state of the signal and their outputs are applied to a comparison circuit (6) so that a word may be verified with one held in a reference memory (7). The end of pulse output pin of each of the registers are connected to a matrix of programmable points.