Multiprocessor arrangement with a common bus.

摘要

A common bus architecture is disclosed which has truly distributed control. A plurality of bus interface units (BIU) are interconnected by the distributed system data bus (DSDB) which includes a clock line (4), a serial command line (CMD), a serial bus allocation line (BAL) and a two byte wide data bus (8). A central clock connected to the clock line which defines the message frame timing, is the only centralized "control" element in the system. Each BIU may in turn be connected to either one or several data processing units, an I/O port, or a bridge connecting to still another similar bus network.
<??>By prior arrangement, several BIUs will establish a set of relative priorities, commands and corresponding data transfer operations. The BIUs share the DSDB in a time division multiple access mode which requires them to agree to a time divided allocation of the common bus based upon their distributed assessment of the relative priorities of their pending messages. When a processor serviced by a first (talker) BIU wants to transmit data over the DSDB to a processor serviced by a second (listener) BIU, a three stage priority contention resolution operation takes place to obtain an exclusive allocation of the DSDB for the desired data transmission.