| 摘要 |
<p>The device detects the synchronisation sequences in serially encoded digital data and comprises the instants of those detections with a previously acquired synchronisation. The synchronisation sequence has N binary elements. A decoder circuit, comprising an N stage shift register, has its outputs connected to a comparator. The comparator also receives synchronisation data elements. The comparator uses majority logic and delivers a control pulse which produces a shift in the synchronisation circuit when there is less than preset number of non-coincidences between the acquired and the detected synchronisations. The circuit obviates the need for random validations in the synchronisation sequences, thus reducing the error rate.</p> |
