发明名称 PHASE SYNCHRONIZATION SYSTEM
摘要 PURPOSE:To generate a clock signal on a two-wire two-way time-division transmission system securely by storing the waveform of a received clock when it is present, and compensating the clock by extracting the stored waveform while the received clock is toothless. CONSTITUTION:From a data train of a time-division transmitted signal arriving via a subscriber system transmission line, a clock is extracted, and a detector DET for a toothless received clock detects time other than the reception of a received signal in transmission line mode. The wavform of the received clock is recorded in a waveform storage circuit MEM and while the received clock is toothless, an input to a phase comparator PC is switched from the received clock to the circuit MEM by a switching control signal generated by the detector DET. Consequently, the toothless part of the received clock is compensated to supply the received clock to the phase comparator PC all the time.
申请公布号 JPS57160225(A) 申请公布日期 1982.10.02
申请号 JP19810045150 申请日期 1981.03.27
申请人 FUJITSU KK 发明人 TOMITA YOSHIHIRO;MURANO KAZUO;UMIGAMI SHIGEYUKI;SOEJIMA TETSUO
分类号 H03L7/14;H03L7/08;H04L7/033 主分类号 H03L7/14
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