发明名称 OPERATING CIRCUIT
摘要 PURPOSE:To reduce the operating time, by using a signal of difference at subtraction and making the division and the multiplication with the 3rd number of the quotinent at the same time, in the operation circuit making multiplication and division through the use of adder/subtractor. CONSTITUTION:Two addition/subtraction circuits are provided. The 1st circuit is used as a subtractor 6-1 for division, and an adder 6-2 of the 2nd adder/ subtractor is controlled with one bit every time the 1-bit of the quotinent is determined and the multiplication is made by this adder 6-2, allowing to make operation processing of (bdivided by c)Xa in a short time.
申请公布号 JPS57189249(A) 申请公布日期 1982.11.20
申请号 JP19810075136 申请日期 1981.05.19
申请人 MITSUBISHI DENKI KK 发明人 KUDOU TSUKASA;FUSAOKA AKIRA
分类号 G06F7/508;G06F7/52 主分类号 G06F7/508
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