| 摘要 |
<p>PURPOSE:To facilitate designing of a clock signal producing circuit and to realize both miniaturization and a high-speed operation of said clock producing circuit, by increasing the strictness of request to the time interval of the clock signals needed for decision among those to be used. CONSTITUTION:Two pre-signals A'0 and -A'0 which are contrary to each other are delivered from a pre-circuit 1 by an address-designated input signal A1 and reference voltage signal VREF and then applied to a primary circuit 2 and furthermore to enhancement type FETQ11-Q16. The outputs of these FETSQs are applied to nodes N9 and N10 which supply a clock signal phi2. Then the signals of these nodes are applied to the gates of enhancement type FETQ17 and Q18, and at the same time a clock signal P1 is applied to the gates of enhancement type FETQ19 and Q20. An FF circuit is formed with these FETQ11-Q16, and a latch circuit is constituted of nodes N9 and N10 and a capacitor C. Then an output signals A0 and -A0 of clocks having strict time intervals are delivered from FETQ17-Q20.</p> |
