发明名称 RESETTNG SYSTEM OF FAULT DETECTING TIMER
摘要 PURPOSE:To start an emergency control circuit even in case of a fault occurring to a reset signal generation part by executing plural instructions for generating characteristic reset signals in prescribed order and monitoring the generation order of the reset signals. CONSTITUTION:A start signal outputted from a counting part 5 at prescribed cycles is transmitted to a counting part 8 and an order part 9. The counting part 8 controls the order part 9 every time when the start signal is received to transfer the received start signal to the 1st and the 2nd instruction execution parts 10 and 11 alternately. The execution parts 10 and 11 while in normal operation transfer the 1st and the 2nd reset signals to an order monitoring part 12 alternately at prescribed cycles. The monitoring part 12 transfers the 1st and 2nd reset signals transferred irregularly by turns to a fault detecting timer 7, which is reset on the reception of every signal, so that the emergency control circuit 2 is never started. When >=2 successive signals are inputted, the monitoring part 12 transfers neither of them to the timer 7, so the timer 7 is never reset and starts the circuit 2 a specific time later.
申请公布号 JPS58140855(A) 申请公布日期 1983.08.20
申请号 JP19820022355 申请日期 1982.02.15
申请人 FUJITSU KK 发明人 TOKUNAGA SHIYUUICHI;OGASAWARA YASUO
分类号 G06F11/30;G06F11/00 主分类号 G06F11/30
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