发明名称 INTER-PROCESSOR COMMUNICATION SYSTEM
摘要 <p>PURPOSE:To simplify a program, improve processing performance and efficiency of a multiprocessor system, by making a processor on the transmission side access a memory in the receiving side processor by using an address in a direct instruction level. CONSTITUTION:Information received from a comunication line 61 is stored in a memory in a processor 50, the address information of a bucket is discriminated, the processor of an output line is decided, and data transmission to a communication processor 10 on the corresponding output line side is started. In the communication processor 10 on the output line side, the output line is discriminated by the information in a transaction buffer area and the bucket information is sent to the corresponding communication line 61. Charging data or the like are collected in the communication processor 10 and sent to a main processor 20 through the transaction buffer and the processed result is written in a magnetic tape device 72.</p>
申请公布号 JPS58144273(A) 申请公布日期 1983.08.27
申请号 JP19820025763 申请日期 1982.02.19
申请人 NIPPON DENKI KK 发明人 TSUKAMOTO TERUO
分类号 G06F15/17;G06F12/06;G06F15/167 主分类号 G06F15/17
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