| 摘要 |
PURPOSE:To reduce the power consumption of an integrated circuit by connecting the drain and gate of an FET directly to a power terminal and using as a power voltage of the integrated circuit the voltage which is obtained from the source. CONSTITUTION:The drain of an N-channel depletion FETQ2 having a threshold voltage VTD is connected to a power source VDD, a substrate and a gate are connected to ground, and a source is connected to a power source VLOG of an integrated circuit 1. Since the gate of an FETQ2 is grounded, a drain current initially flows, but the source voltage rises until the voltage difference VSG between the source and the gate becomes equal to -VTD. Since the relationship between the voltage difference VBS between the substrate and the source of the FET and the VTD is as designated by a curve 2, it becomes VBS=VTD, and this characteristic results in that -VTD at the crossing pint E is the voltage C. Since the power source voltage is not by VDD and always by the constant voltage between the VDD and the ground in the circuit 1, the operation with low power consumption can be performed. |
