| 摘要 |
PURPOSE:To perform arithmetic at a high speed, by providing a multiplication bus dedicated to data transfer among plural unit processors to a circuit which uses the plural unit processors to multiply data whose lengths are integral multiples of a basic word length by each other. CONSTITUTION:The unit processors UP1-1-UP1-n incorporate multipliers with the basic word length, and function to multiply data whose lengths are integral multiples of the basic word length by each other under the control of a controller 2. The multiplication bus 4 dedicated to data transfer is provided among the UPs 1-1-1-n, which perform the transfer, etc., of the transfer multiplication result of data for multiplication between the high-order and low-order digit bits of a multiplier and a multiplicand through the bus 4 without the intervention of the CT2. Consequently, the data whose lengths are integral multiples of the basic word length are multiplied easily by each other and the multiplication is speeded up. |
