| 摘要 |
PURPOSE:To shorten a manufacturing period by previously forming a wiring to the gate array and etching the wiring in response to specifications. CONSTITUTION:A P well region 2, a P channel element region 3 and an N channel element region 4 are formed to an N type semiconductor substrate 1, and gate electrodes 51, 52 and source or drain regions 31, 32, 33, 41, 42, 43 are formed, thus forming a pair of MOS transistors. Contact holes 211-216 are formed, Al is evaporated on the whole surface, Al wirings 221, 222, 231, 232, 233, 24 are formed through etching, and a PSG film is formed to the whole surface through a CVD method. The PSG film on the Al wirings 221, 222, 231-233, 24 is etched selectively according to specifications from users at the stage, the Al wirings exposed are removed through etching while using residual PSG films as masks, and various logic circuits are constituted. |
