发明名称 |
Semiconductor memory devices |
摘要 |
In a semicondcutor memory device there is provided a specific layout of each element effectively excluding a number of "bridge" crossings for specific lines connecting the elements particularly buffer circuits and a decoder circuit, and thereby reducing the amount of resistance in the lines connecting specific elements, and increasing the signal transmission speed in the specific lines. A control circuit is arranged either beneath or above a portion of the ground line or the electric power line and the control circuit is connected to either of these lines by further vertical lines, thereby eliminating certain bridges. |
申请公布号 |
US4439841(A) |
申请公布日期 |
1984.03.27 |
申请号 |
US19810272367 |
申请日期 |
1981.06.10 |
申请人 |
FUJITSU LIMITED |
发明人 |
ITOH, HIDEO;YAMAUCHI, TAKAHIKO |
分类号 |
G11C11/41;G11C5/02;G11C5/14;G11C11/401;H01L21/822;H01L23/528;H01L27/02;H01L27/04;H01L27/10;(IPC1-7):11C13/00 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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