| 发明名称 |
CMOS INTEGRATED CIRCUIT WITH GUARD BANDS FOR LATCH-UP PROTECTION |
| 摘要 |
Latch-up in bulk CMOS integrated circuits, caused by a parasitic pnp and npn transistors, is prevented by use of p-plus (42) and n-plus (44) guard bands which are juxtapositioned and connected to a common power supply (Vdd). |
| 申请公布号 |
WO8401241(A1) |
申请公布日期 |
1984.03.29 |
| 申请号 |
WO1983US01420 |
申请日期 |
1983.09.19 |
| 申请人 |
SEMI PROCESSES, INC. |
发明人 |
DENHAM, PAUL;ALLEN, PATRICK, CHARLES |
| 分类号 |
H01L29/78;H01L27/08;H01L27/092;H01L29/06;(IPC1-7):01L27/02 |
主分类号 |
H01L29/78 |
| 代理机构 |
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代理人 |
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