发明名称 COMPLEMENTARY TYPE METAL OXIDE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To increase the degree of integration, and to improve yield by forming metallic wiring layers of three layers including a gate electrode. CONSTITUTION:A silicon oxide film is formed thinly on the surface of an N type silicon substrate 1, and a P well region 2 is formed. Sections corresponding to the source region 6 and drain regions 6' and 6'' of an N channel MOS transistor formed in the P well 2 are bored in the oxide film 4, and the ions of an N type impurity such as arsenic are implanted from the openings, thus changing these regions into N<+> regions. Likewide, sections corresponding to the source region 7 and drain region 7' of a P channel MOS transistor formed in the N type substrate 1 and a P well potential extracting port 8 in the P well 2 are bored in the oxide film 4, and the ions of a P type impurity such as boron are implanted, thus changing these regions into P<+> regions. One part of the oxide film 4 in the upper section of the P well potential extracting port 8 in the P well 2 and the source region 6 adjacent to the port 8 is bored, and a ground wire 10 consisting of a film made of aluminum and a silicon alloy and a titanium film is formed.
申请公布号 JPS59121970(A) 申请公布日期 1984.07.14
申请号 JP19820228042 申请日期 1982.12.28
申请人 TOSHIBA KK 发明人 NOZAWA HIROSHI
分类号 H01L21/8238;H01L27/092;H01L29/78 主分类号 H01L21/8238
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