| 摘要 |
PURPOSE:To reduce contact resistance in a contact section, and to stabilize the title integrated circuit device by bringing a polycrystalline silicon layer as a lower layer forming a poly-sided wiring and a polycrystalline silicon wiring as an upper wiring into contact on the side of the poly-side wiring. CONSTITUTION:A field oxide film 2 and a gate oxide film 3 are formed on a P type single crystal Si substrate 1, a polycrystalline silicon layer 4 is formed and a silicide layer 5 is shaped, and a wiring is formed through photoetching. An N<+> diffusion layer 6 is formed through ion implantation, and an inter-layer insulating film 7 is shaped. One part of the inter-layer insulating film 7 is removed so that an oversize is obtained on at least one side of a poly-sided wiring, and a contact hole for a connection is bored. A polycrystalline silicon layer 8 is formed on the contact hole, and a wiring is formed by selective removal through photoetching. Accordingly, the polycrystalline silicon layer 4 as the lower layer of the poly-sided wiring and the polycrystalline silicon layer 8 as an upper wiring are brought in contact directly on the side of the poly-sided wiring. An inter- layer insulating film 9 is formed, a contact hole is bored, and an Al wiring 10 is formed on the contact hole. |
