| 摘要 |
PURPOSE:To allow the system to cope with break even if break is applied by any of a transmission and a reception frequency by shifting a keying signal and a transmission timing so as to receive alternately or at random the transmission frequency and the reception frequency. CONSTITUTION:In depressing a key K, a terminal 8 goes to an H level via an OR gate G8 and a CPU connected to the terminal 8 discriminates it as the transmission and receives the transmission frequency. However, a transistor (TR) Q6 is turned off with a delay by time constants R2C1, R3C9, a reception circuit connected to a terminal 3 is muted and the transmission frequency is received. Moreover, the signal is subject to delay by a time constant R4C2 so as to turn on TRs Q9, Q8, Q7 and Q5, a voltage is applied to terminals 2, 2', the signal is delayed by time constants R19, C5, and R23, C7 and transmitted to a terminal 5 while the transmission muting is released. Even if the key K is released, the terminals 2, 8 are at an H level, the state is in the transmission state, the reception circuit at a terminal 3 receives the signal of the transmission frequency, and when the terminal 3 goes to an L level, the terminal 8 goes to an L level, the frequen cy becomes the reception frequency and the recption circuit receives the signal of the reception frequency. |
