Fast multiplier structure in MOS integrated circuits

摘要

The invention relates to a fast multiplier structure in MOS integrated circuits. In this structure only basic multipliers such as 170, 161... and carry look ahead or fast carry propagation adders 1 to 8 are used. The partial products are added by first-level adders 1 to 4 grouping the columns of the matrix of multipliers in twos. The sums obtained are added by second-level adders 5 and 6, whose outputs are added by a third-level adder 7. A final adder 8 assembles the final carries from the first adders 1 to 7 and the intermediate results of the same significance such as the sums 908 to 910, 711-5... The invention applies to fast integrated multipliers. <IMAGE>