Radiation hardened digital circuit

摘要

This disclosure relates generally to radiation hardened digital circuits. In one embodiment, a radiation hardened digital circuit includes a delay network and a first Muller C element. The delay network is configured to generate a first delayed clock signal from a global clock signal such that that the first delayed clock signal is delayed with respect to the global clock signal. The first Muller C element is configured to generate a first clock input signal and set the first clock input signal to one of a set of clock states in response to the first delayed clock signal and the global clock signal each being provided in a same one of the set of clock states and is configured to hold the first clock input signal otherwise. Thus, a radiation strike is prevented from causing a soft error in the first clock input signal.

主权项

1. A radiation hardened digital circuit, comprising:
a delay network configured to receive a global clock signal and generate a first delayed clock signal from the global clock signal such that the first delayed clock signal is delayed with respect to the global clock signal; and a first Muller C element configured to receive the global clock signal and the first delayed clock signal, wherein the first Muller C element is configured to:
generate a first clock input signal;set the first clock input signal to one of a set of clock states in response to the first delayed clock signal and the global clock signal each being provided in a same one of the set of clock states, wherein the set of clock states comprises a first clock state and a second clock state; andhold the first clock input signal in the one of the set of clock states in response to the first delayed clock signal and the global clock signal being provided in different ones of the set of clock states.