发明名称 Frequency synthesizer using an arithmetic frequency synthesizer and plural phase locked loops
摘要 A frequency synthesizer for controlling the frequency f0 of a signal e0 in response to a control signal ec2 to produce a band of selectable frequencies separated by DELTA f between the frequencies fx and fy, where (fx+R DELTA f)=f0 and R is zero or any integer </=(fy-fx)/ DELTA f. The invention includes a first generator for generating the signal e0, a second generator for generating a signal e1 having a band of selectable frequencies separated by delta f, where delta f>> DELTA f, a frequency subtractor for subtracting f1 from f0 to produce a signal e2 of frequency f2. Also provided is a third generator for generating a variable preliminary reference signal of frequency fpr consisting of a band of selectable frequencies separated by M DELTA f and lying within the frequency band Mfx to Mfy, where (Mfx+RxM DELTA f)=Mfr2; a divider for dividing Mfr2 by M to produce a band of signal frequencies (fx+R DELTA f)=fr2; and a comparator for comparing f2 with fr2 to produce the control signal ec2.
申请公布号 US4516084(A) 申请公布日期 1985.05.07
申请号 US19830467644 申请日期 1983.02.18
申请人 RCA CORPORATION 发明人 CROWLEY, ALBERT T.
分类号 H03L7/23;(IPC1-7):H03L7/00 主分类号 H03L7/23
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