| 摘要 |
<p>PURPOSE:To improve the processing speed of the titled device by dividing a pipe line into a self-system and the other system to prevent the access of the other CPU in the self-system from being waited when one CPU in the self-system accesses the other system. CONSTITUTION:Receiving an access from a CPU0 by an interface register 1, a storage control device MCU0 selects the signal by an access selecting circuit S2 and sends the signal to a MCU1 through a port P6. On the MCU1 side, the access signal sent by said procedure is received by an interface register P13, sent to a main storage MSU2 through an access selecting circuit S1i and a port P14 and also inputted to a pipe line PL11. Synchronously with the transmission of read data from the MSU2 to the port P8, the storage access of a pipe line PL2 actuates a control part DC1 and transfers data in the port P8 to the CPU0 through a selector S4a and port P9a.</p> |
