| 摘要 |
Digital phase-locked loop circuit for telecommunication circuits receiving bipolar codes (1). The digital phase-locked loop circuit includes a transition timer circuit (20) for counting a transition time between a high mark and a low mark in said bipolar code (1). A clock recovery signal is generated (30) by dividing a transition time by a value, such as two, to indicate an apparent zero crossing time, and comparing (30) the apparent zero crossing time with the reference clock (50) in the circuit receiving the bipolar code (1). The reference clock (50) in the receiving circuit is adjusted (40) in response to the clock recovery signal in order to maintain the reference clock (50) substantially in phase with the incoming bipolar code (1). |
