| 摘要 |
<p>In a dynamic RAM, the refreshing operation is performed during one cycle of the read or write operation. A switch circuit (SW1, SW2) selects either a row address signal output from address input circuit (17) or a refresh row address signal output from a refresh circuit (19). By controlling the switch circuit (SW1, SW2) by a switch selector (20), the refresh is performed during the operation delay time of the address input circuit (17) or an input/output circuit (18) for inputting and outputting data.</p> |
