| 摘要 |
PURPOSE:To reduce the load of a processor by providing a busy bit to each minor block to unify the writing/reading orders of minor blocks at all writing and reading sides and therefore checking the next minor block in case the continuous data are processed. CONSTITUTION:Masters 1 and 2 are connected to each other via a shared memory 3, and the memory 3 consists of minot blocks 10-13. Then bits 20-23 showing the busy states are provided to the blocks 10-13 respectively. Thus a shared memory control system is obtained. The same order is secured by the masters 1 and 2 for writing and reading of connection data to the blocks 10-13. Then the busy states of bits 20-23 are checked before the writing and reading are carried out to the head block 10. If the bits 20-23 are already set, another master 1 or 2 is set before the reset state is detected. While the bits 20-23 are monitored continuously until they are reset when they are set. Then the bits 20-23 are set when they are reset respectively. |
