Data delay/memory circuit.

摘要

A data delay/memory circuit includes clock-controlled data latch circuits formed with cascade-connected clocked inverters (11-17). The data delay/memory circuit also includes a clock generator (CG) for supplying the clocked inverters (11-17) with clock signals (φ1-φ7, φ1-φ7). These clock signals (φ1-φ7, φ1-φ7) have individual clocking phases and are sequentially generated such that the clocking phase for a final stage (17) of the data latch circuits is ahead of that for an initial stage (11) thereof.