| 摘要 |
PURPOSE:To increase greatly the processing speed of an input signal by applying the clock signals and their reverse signals to a switching means every second stages. CONSTITUTION:The clock signal phi1 is applied from a common line 12 to each gate of transistors Tr 10, 12 and 14 of every two Trs respectively. While OR gates G1...Gi are provided to the stages S1...Si respectively. While the clock signal phi2 of a common line 13 is applied to the inputs of one sidfe of gates G1, G3,..., i.e., every second one included in output stages S1, S3,..., i.e., every second one of the OR gate G. Then the inverted outputs of inverters INV11, INV13,... included in the stages S1, S3,... are applied to the inputs of the other side of the gate G. In addition, the signal phi1 of the line 12 is applied to the inputs at one side of the gate G2, G4,... provided to the rest output stages S2, S4,..., i.e., every second one. Then the outputs of inverters INV12, INV14,... included in the stages S2, S4,... are applied to the inputs of the other side of the gate G respectively. |
