发明名称 |
METHOD FOR MANUFACTURING VLSI COMPLEMENTARY MOS-FIELD EFFECT TRANSISTOR CIRCUITS |
摘要 |
<p>A method for manufacturing a CMOS circuit wherein a process sequence matched to an n-tub manufacture is carried out. Short-channel properties of n-channel transistors are improved by performing double boron implantations of the channel regions. A shared channel implantation is executed for both transistor types. Compared to traditional CMOS processes in n-tub structure, this eliminates involved masking steps. Also, the polysilicon gate is shielded from the boron ion implantation by means of a masking re-oxidation step and the under-diffusion given n-channel an p-channel transistors is greatly reduced by means of pull-back of the boron source/drain implantation. This contributes significantly to a symmetrical UT behavior of the transistors and to the attainment of high switching speeds. The method is used in the manufacture of VLSI CMOS circuits in VLSI technology.</p> |
申请公布号 |
CA1211865(A) |
申请公布日期 |
1986.09.23 |
申请号 |
CA19840452430 |
申请日期 |
1984.04.19 |
申请人 |
SIEMENS AKTIENGESELLSCHAFT |
发明人 |
JACOBS, ERWIN P.;SCHWABE, ULRICH |
分类号 |
H01L27/092;H01L21/265;H01L21/8234;H01L21/8238;H01L27/08;H01L27/088;H01L29/78;(IPC1-7):H01L21/82 |
主分类号 |
H01L27/092 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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