| 摘要 |
PURPOSE:To shorten the writing time by providing a data register for each common column line containing a prescribed number of column lines for storage of the write data and at the same time writing these write data on plural memory cells. CONSTITUTION:When only a column address YA0, for example, is set at H, the data to be written from a data input buffer 3' are stored in a register R1. In the same way, data are stored in other registers. Then the data stored in the registers R1-R4 are supplied to the gates, and transistors QA0-QA4 are turned on or off in response to those data. Thus common column lines CL1-CL4 for eight column lines cl10-cl17 and cl40-cl47 respectively are set at each level of writing voltage in response to the write data. Then the writing operations are carried out simultaneously to ROM cells MC of four pieces, for example, and the data writing time is shortened.
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