| 摘要 |
<p>PURPOSE:To perform writing of multiple bits at a high speed, by installing a latch circuit and level transducing circuit which forms a voltage necessary for making writing/erasing operations to each data line of a memory array. CONSTITUTION:The memory cell of a memory array M-ARY is composed of a MOSFET Q1 for address selection, MNOS transistor Q2 acting as a semiconductor nonvolatile memory element and MOSFET Q3 for separation. A latch circuit FF for holding previously stored information and rewriting information before making erasing/writing operations and a level transducing circuit LVC which selectively sets the level of a data line to a negative high voltage -Vpp in accordance with stored information for writing operations are provided to each data line D1 and D2. When Y addresses are switched, the information held by the corresponding latch circuit FF is replaced with write signals supplied from an external terminal and writing operations are executed at once to memory cells of one word quantity.</p> |
