| 摘要 |
<p>PURPOSE:To simplify an address decoder circuit, by providing a level converting circuit which changes the electric potential of the 2nd word line coupled with a storage element upon receiving the selected level of the 1st word line coupled with a MOSFET for address selection. CONSTITUTION:Each of memory cells MS11-MS22 is composed of a MOSFET Q2 for address selection and MNOS Q1 acting as a storage element. The NOR gate G1 of an address decoder circuit UXDC constituting an X-address decoder forms a word line selecting signal upon receiving an address signal and a level inverting circuit composed of CMOS inverter circuits Q3 and Q4, transmission gate MOSFETs Q5 and Q6, and CMOS inverter circuits Q7 and Q8 selectively inverts the output signal of the circuit G1 by using a control signal W which distinguishes writing operations from erasing operations. The output terminal of the address decoder UDEC is coupled with the 1st word line W11 and a level converting circuit LVC which determines the electric potential of the 2nd word line W12 in accordance with the level of the 1st word line W11 is provided.</p> |
