| 摘要 |
PURPOSE:To attain the interchangeability with a varying speed CPU by using a means which delays substantially the access start to an input and output I/O device. CONSTITUTION:An OR circuit 17 secures an OR of an I/O write signal 5 of negative logic as well as an I/O read signal 4 of negative logic. Then a flip-flop F/FA 18 is preset to obtain an I/O access detecting signal 8. While an F/FB 19 secures the synchronism with the working of a CPU 1 by means of an address latch signal 6. The signals QA-QH having shifts by a single clock respectively are obtained by a shift register 20. These signals are combined to obtain a gate signal 11 and a wait signal 10 of negative logic. Thus the access interval tRV can be delayed for the continuous accesses of an I/O device 3. Then the conventional software is available with no alteration.
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