Disclosed is a digital signal processor. The digital signal processor comprises: a signal generation unit configured to generate a first digital signal and a second digital signal; a first modulation unit configured to modulate the first digital signal to obtain a third digital signal; a second modulation unit configured to modulate the second digital signal to obtain a fourth digital signal; a first phase shift unit configured to perform a phase shift on the third digital signal to output the third digital signal and a fifth digital signal; a second phase shift unit configured to perform a phase shift on the fourth digital signal to output the fourth digital signal and a sixth digital signal; an adder configured to sum the third digital signal and the fourth digital signal to obtain a seventh digital signal configured to drive a first drive signal of a single sideband modulator; and a subtractor configured to subtract the sixth digital signal from the fifth digital signal to obtain an eighth digital signal configured to drive a second drive signal of the single sideband modulator. An embodiment of the present invention doubles a frequency spectrum utilization ratio and device broadband usage.
