Method filling interlevel dielectric via or contact holes in multilevel VLSI metallization structures.

摘要

A method compatible with very large scale integrated circuit fabrication processes is employed to provide an electrical connection between conductive layers separated by an insulative layer in integrated circuit devices. An intermediary metal such as molybdenum or tungsten is deposited by one or more methods so as to fill an opening in the insulative layer. A planarization resist may be applied on the substrate and the resulting configuration is planarizingly etched down to the insulative layer so as to provide a metal plug serving as an electrical contact between upper and lower conductive layers. Deposition is by sputtering, evaporation, or by either selective or non-selective chemical vapor deposition. The process and structure provided herein significantly alleviates step coverage problems associated with aluminum and like materials which do not readily penetrate small VLSI circuit openings.