| 摘要 |
PURPOSE:To speed up arithmetic processing and to easily set the operation timing of each circuit by composing each circuit of a static circuit and cascading plural arithmetic circuits by using plural data buses and selectors. CONSTITUTION:An adder subtracter 27 which performs the addition and subtraction of the exponent part of floating point data, an adder subtracter 45 which performs the addition and subtraction of the mantissa part of said data, a multiplier 28, shift circuits 39, 42, and 55, registers 20, 21, and 40, and selectors 23, 24, 30, 32, 47, and 51 are composed of static circuits. Further, those arithmetic circuits (adder subtracters, multiplier and shift circuits) are cascaded by using plural data buses 25, 31, 41, 43, 44, 46, 50, and 56 and selectors 23, 24, 30, 32, 47, and 51. The respective circuits are the static circuits, so it is not necessary to provide the time for precharging, and the connection order of the respective arithmetic circuits is changed optionally by the selector, so the operation of each circuit is performed without any wait time and the arithmetic processing is speeded up. |
