| 摘要 |
A memory addressing system utilizing translated memory address information includes a microprocessor (20), a memory management unit (52) adapted to translate addresses, a cache memory (26) which stores data information and tag information, and a main memory (19). The cache memory (26) is addressed by a 23-bit word which includes a 12-bit index address portion and an 11-bit tag portion. The two most significant bits of the index address portion are stored in a flip-flop device (76). During the next memory cycle the cache memory (26) is addressed using the untranslated least significant 10 bits of the index address together with the two stored bits to provide rapid addressing. The two stored bits are compared in a comparator (80) with the corresponding two new bits after translation, and the cache memory (26) output is utilized for a further comparison if the comparison result is equal. Otherwise, the main memory (19) output is utilized as the system output. The further comparison in a comparator (98) between the new tag information and the tag information read out from the cache memory (26) further determines whether the cache memory (26) or the main memory (19) is utilized for the system output. |
