发明名称 |
Semiconductor memory device having serial addressing scheme |
摘要 |
A semiconductor memory of the type that a plurality of memory locations are sequentially addressed in synchronism with a chain of clock pulses without externally applied address signals is disclosed. The memory is provided with a detection circuit for detecting a selection of a predetermined memory location and thus it is allowed for user to know which memory location has been addressed.
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申请公布号 |
US4802134(A) |
申请公布日期 |
1989.01.31 |
申请号 |
US19860944115 |
申请日期 |
1986.12.22 |
申请人 |
NEC CORPORATION |
发明人 |
TSUJIMOTO, AKIRA |
分类号 |
G11C7/00;G11C7/10;G11C11/401;G11C11/407;G11C11/4096;G11C11/413;(IPC1-7):G11C7/00;G11C8/00;G11C11/40 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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