| 摘要 |
<p>Two buffer circuits of FIFO type, connected together in anti-parallel mode, form a bi-directional message buffer. Communications between the processors is via data busses and input/output circuits. The unit contains two status registers and two command registers. Each status register operates on 8-bit words, the first bit of which indicates whether a message from its associated processor is available. Each command register operates on an 8-bit word. the second bit of which indicates that a meassage has been received. When the message received bit is set it automatically resets the message available bit in the status register.</p> |
