DELAY CIRCUIT FOR GATE ARRAY

摘要

The delay circuit has at least one inverter having the several P- channel transistors (Q1P-Q4P) connected in series between a power supply (VCC) and an output terminal and the several N-channel transistors (Q1N-Q4N) connected in series between the output and the second power terminal (GND). The P-channel transistors are operable to be sequentially turned on from the outside to the inside by a fall of potential at an input terminal and vice-versa for a rise of potential. The N-channel transistors are sequentially turned on from outside to the inside by a rise potential at the input and vice- versa.