KOMMUNIKATIONSDATAMAT TIL ET PAKKE-OMSKIFTET KREDSLOEB

摘要

A packet switch has a number of processing units 17-1, 17- N for gathering data received at an input for the packets, and a memory 10 to store the data packets, and a bus 20 to enable communication between each of the processing units and the memory. An arbitrator 42 in a packet-switch determines which of the processing units will be granted access to the bus, and it is programmable to selectively or alternately designate each of at least two different levels of access priority to the bus for each of the processing units, in order to assure greater access to the bus for the processing units which have the highest priority level. This achieves selective access to the memory via the bus in any given number of types of bus cycles, including a read cycle, a write cycle, and a read/modify/write cycle, each cycle having a request phase and a reply phase.