| 摘要 |
<p>In a phase detection circuit for detecting the phase relation between a first (f1) and a second (f2) clock signal in which tappings (b, c, d, e, f, g, h, i) of a delay circuit (7) for the first clock signal are connected to memory elements (27, 29, 31, 33, 35, 37, 39, 41) clocked by the second clock signal and having their outputs (B, C, D, E, F, G, H, I) connected to a logic circuit (59) and in which a plurality of outputs of the delay circuit (7) is connected to a measuring circuit (89, 95) for measuring the delay time of the delay circuit, a control circuit (87, 85, 93, 91, 83, 77, 79, 81) controlled by the measuring circuit is arranged for controlling the delay time of the delay circuit at a value corresponding to the period of the first clock signal, while the logic circuit comprises an AND-gate (61, 65, 69, 73) alternating with a NOR-gate (63, 67, 71, 75) for obtaining a very accurate and unambiguous phase detection, using few circuit elements.</p> |
