| 摘要 |
<p>A semiconductor memory device including: a RAM portion; a shift register for enabling parallel transfer of a one word line amount of data of the RAM portion between the RAM portion and the shift register, the shift register being divided into a plurality of shift register portions, serial input data being distributed alternately between the shift register portions by the operation of a multiplexer (MULTIPLEXER 1), serial output data being obtained by picking up data alternately from the shift register portions by the operation of another multiplexer (MULTIPLEXER 2); a transfer gate portion (T3, T4) inserted between the RAM portion and the shift register for carrying out parallel transfer, the transfer gate portion consisting of a plurality of groups of transfer gates for enabling selective connections of input and output terminals of each of stages of the shift register portions with either of the adjacent odd number bit line and even bit line of the RAM portion, the plurality of transfer gate groups being switched in correspondence with shift clock signlas.</p> |
