SPEICHER FUER VIDEOSIGNALE

摘要

The described memory is intended for video signals whose picture information is partitioned into fields and in which the information of the fields is arranged in lines. Separate field information components may be absent in the video signals to be stored. When fields are read from this store, they should be separated from one another by a vertical blanking interval. To avoid an elaborate write-read control for the memory and to simultaneously provide the possibility of connecting an interpolation circuit (IP) to it, with which the proximity values for the omitted fields are gained, a series arrangement of three shift registers (SR1, l SR2, SR3) is provided. A counter (ZW) generates and counts the shift pulses for the shift registers (SR1, SR2, SR3). Either the data of an incoming field (E1) or the data (E3) of the field stored in the third shift register (SR3) are applied to the first shift register (SR1) via a first controllable switch (U1). In a third position of the controllable switch (U1) the data (E2) of an interpolation circuit (IP) are applied to the first shift register (SR1), which circuit generates the data of an omitted field from the two neighboring fields by interpolation. The completed video signal arranged in a predetermined frame can be derived from an output (A) of the circuit.