| 摘要 |
PROBLEM TO BE SOLVED: To make emulatable an interface control signal with precise timing. SOLUTION: Since the delay time of an RD (read enable) signal can be controlled to an optimum value by switching a selection signal 8 by adjusting it to the power voltage of a user system 4, precise emulation can always be executed. A selection circuit 7 is controlled in such a way that the output delay signal of a delay circuit 61 is selected when the power voltage of the user system 4 is 5 V and the output delay signal of a delay circuit 6, is selected when the power voltage of the user system 4 is 1.8 V if the delay time of the delay circuit 61 is designed to become 2ns and the delay time of the delay circuit 6n to become 8ns. Thus, the actual timing of the interface control signal can precisely be emulated. |
