Non-volatile memory - has sleep mode at lower voltage and novel storage cell

摘要

The storage cell of this novel mass memory is based on the use of a special NPN transistor (Q1) whose base current becomes negative in certain circumstances due to novel impurity radios employed. The current inversion is used in forming a memory cell. The NMOS transistor Q3 serves as a switch element and is controlled by a ''word select'' line (WL). The voltage input to the base of the storage transistor (Q1) is controlled by the ''Bth Select'' line, (BL). The Collector Voltage is lowered after the Write in phase, to save power.